Folks,
Let's assume the following : R2=0 R3=a positive value (Bit 0=0) R14=1 DR 2,14 works R2=0 R3=a negative value (Bit 0=1) R14=1 DR 2,14 leads to a PIC 9 (Fixed point divide exception) I don't see how a DR with RX=0,RX+1=Any value and RY=1 can lead to a fixed point divide exception. Am I missing something ? Thanks, --Ivan [Non-text portions of this message have been removed] |
It might be that the quotient cannot be expressed as a 32bit signed integer
when negative, which would give a PIC 9. Joe On Fri, Apr 7, 2017 at 3:42 PM, Ivan Warren [hidden email] [hercules-390] <[hidden email]> wrote: > > > Folks, > > Let's assume the following : > > R2=0 > R3=a positive value (Bit 0=0) > R14=1 > DR 2,14 works > > R2=0 > R3=a negative value (Bit 0=1) > R14=1 > DR 2,14 leads to a PIC 9 (Fixed point divide exception) > > I don't see how a DR with RX=0,RX+1=Any value and RY=1 can lead to a > fixed point divide exception. > > Am I missing something ? > > Thanks, > > --Ivan > > [Non-text portions of this message have been removed] > > > |
In reply to this post by Hercules390 - General mailing list
---In [hidden email], <ivan@...> wrote :
> R2=0 > R3=a negative value (Bit 0=1) > R14=1 > DR 2,14 leads to a PIC 9 (Fixed point divide exception) > I don't see how a DR with RX=0,RX+1=Any value and RY=1 can lead to a > fixed point divide exception. Just speculation ... I was under the impression that DR produced a quotient and remainder in the two register field. So dividing 0x0000 0000 ffff ffff by 1 would produce a quotient of 0xffff ffff and a remainder of 0. I think 0xffff ffff is too much like overflow, as it is an unsigned value trying to be stored into what I assume is a signed register. BFN. Paul. |
In reply to this post by Hercules390 - General mailing list
People,
Ignore the previous message. I figured it out. My bad. The z/Arch POP says : The sign of the quotient is determined by the rules of algebra, and the remainder has the same sign as the dividend, except that a zero quotient or a zero remainder is always positive. When the divisor is zero, or when the magnitudes of the dividend and divisor are such that the quotient cannot be expressed by a 32-bit signed binary integer, a fixed-point-divide exception is recognized. This includes the case of division of zero by zero. If RX is 0, RX+1 has bit 0 set to 1, and RY is 1 then the quotient which then should be positive, cannot be expressed as a 32 bit signed integer. So the PIC 9 is warranted. My apologies. --Ivan On 4/7/2017 10:42 PM, Ivan Warren [hidden email] [hercules-390] wrote: > Folks, > > Let's assume the following : > > R2=0 > R3=a positive value (Bit 0=0) > R14=1 > DR 2,14 works > > R2=0 > R3=a negative value (Bit 0=1) > R14=1 > DR 2,14 leads to a PIC 9 (Fixed point divide exception) > > I don't see how a DR with RX=0,RX+1=Any value and RY=1 can lead to a > fixed point divide exception. > > Am I missing something ? > > Thanks, > > --Ivan > > > > > [Non-text portions of this message have been removed] > > > > ------------------------------------ > Posted by: Ivan Warren <[hidden email]> > ------------------------------------ > > Community email addresses: > Post message: [hidden email] > Subscribe: [hidden email] > Unsubscribe: [hidden email] > List owner: [hidden email] > > Files and archives at: > http://groups.yahoo.com/group/hercules-390 > > Get the latest version of Hercules from: > http://www.hercules-390.org > > > ------------------------------------ > > Yahoo Groups Links > > > [Non-text portions of this message have been removed] |
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On 4/8/2017 12:14 AM, Joe Monk [hidden email] [hercules-390] wrote: > > > It might be that the quotient cannot be expressed as a 32bit signed > integer when negative, which would give a PIC 9. > > Joe > Sorry, I was thinking this wrong. R2=0 R3= <any value with bit 0 set to 1> Is still a positive value for DR (The Dividend is RX *AND* RX+1 - as 32 bit registers) .. It would be negative if R2 had bit 0 set to 1 ! Duh ! So a DR with Rx=0, RX+1 with bit 0 set to 1 and Ry = 1 has to give a PIC 9 .. Apolologies. --Ivan [Non-text portions of this message have been removed] |
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Hey man ... no worries :)
Everyone (including me, as you've seen) sometimes has brain farts :) Joe On Fri, Apr 7, 2017 at 5:15 PM, Ivan Warren [hidden email] [hercules-390] <[hidden email]> wrote: > > > People, > > Ignore the previous message. > > I figured it out. My bad. > > The z/Arch POP says : > > The sign of the quotient is determined by the rules of > algebra, and the remainder has the same sign as the > dividend, except that a zero quotient or a zero > remainder is always positive. > When the divisor is zero, or when the magnitudes of > the dividend and divisor are such that the quotient > cannot be expressed by a 32-bit signed binary integer, > a fixed-point-divide exception is recognized. This > includes the case of division of zero by zero. > > If RX is 0, RX+1 has bit 0 set to 1, and RY is 1 then the quotient which > then should be positive, cannot be expressed as a 32 bit signed integer. > So the PIC 9 is warranted. > > My apologies. > > --Ivan > > On 4/7/2017 10:42 PM, Ivan Warren [hidden email] [hercules-390] wrote: > > Folks, > > > > Let's assume the following : > > > > R2=0 > > R3=a positive value (Bit 0=0) > > R14=1 > > DR 2,14 works > > > > R2=0 > > R3=a negative value (Bit 0=1) > > R14=1 > > DR 2,14 leads to a PIC 9 (Fixed point divide exception) > > > > I don't see how a DR with RX=0,RX+1=Any value and RY=1 can lead to a > > fixed point divide exception. > > > > Am I missing something ? > > > > Thanks, > > > > --Ivan > > > > > > > > > > [Non-text portions of this message have been removed] > > > > > > > > ------------------------------------ > > Posted by: Ivan Warren <[hidden email]> > > ------------------------------------ > > > > Community email addresses: > > Post message: [hidden email] > > Subscribe: [hidden email] > > Unsubscribe: [hidden email] > > List owner: [hidden email] > > > > Files and archives at: > > http://groups.yahoo.com/group/hercules-390 > > > > Get the latest version of Hercules from: > > http://www.hercules-390.org > > > > > > ------------------------------------ > > > > Yahoo Groups Links > > > > > > > > [Non-text portions of this message have been removed] > > > |
The usual way to use DR is to load a 32 bit value in register X, and SRDA X,32. This sign extends it to 64 bits.
It should still fail if you divide X'80000000' by X'ffffffff' |
The point is that the divisor is signed 64 bit and the result is signed
32 bit. Since the division by 1 of Ivan's number requires 33 bits to be expressed as a signed integer, you have the overflow. |
In reply to this post by Hercules390 - General mailing list
keep in mind how the registers are paired in Divide and Multiply in Assembler. The pairing order is R0 and R1; R2 and R3; R4, and R5; in other words even and odd pair which is important. Doing odd and even pair does not work and results in the problem you are confronted with.
regards; Rahim Azizarab |
On 4/8/2017 5:47 PM, Rahim Azizarab [hidden email] [hercules-390] wrote: > > > keep in mind how the registers are paired in Divide and Multiply in > Assembler. The pairing order is R0 and R1; R2 and R3; R4, and R5; in > other words even and odd pair which is important. Doing odd and even > pair does not work and results in the problem you are confronted with. > Rahim, That wasn't the issue. Had I used an Odd-Even pair as the dividend for DR, I would have raised a Specification Exception, not a Fixed Point Divide Exception (and the contents of the registers would have been irrelevant). But thanks anyway, --Ivan [Non-text portions of this message have been removed] |
In reply to this post by Hercules390 - General mailing list
Rahim, the DR exception was that the result would not fit into result register. He divided by "00000000 FFFFFFFF" (4294967295) by 1. Remember this is not negative because the high register is 0 (negative numbers have thee first bit on). The results must fit into a single reg which can from -2147483647 to 2147483647. Clearly the number won't fit.
Jon. On Saturday, April 8, 2017 8:47 AM, "Rahim Azizarab [hidden email] [hercules-390]" <[hidden email]> wrote: keep in mind how the registers are paired in Divide and Multiply in Assembler. The pairing order is R0 and R1; R2 and R3; R4, and R5; in other words even and odd pair which is important. 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